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93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
FIGURE 1-1:
CS
V IH
SYNCHRONOUS DATA TIMING
V IL
V IH
T CSS
T CKH
T CKL
T CSH
CLK
V IL
DI
V IH
T DIS
T DIH
DO
(Read)
DO
(Program)
V IL
V OH
V OL
V OH
V OL
T SV
T PD
Status Valid
T PD
T CZ
T CZ
Note:
T SV is relative to CS.
TABLE 1-3: INSTRUCTION SET FOR X16 ORGANIZATION (93XX56B OR 93XX56C WITH ORG = 1 )
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
ERASE
1
11
X
A6 A5 A4 A3 A2 A1 A0
—
(RDY/ BSY )
11
ERAL
EWDS
EWEN
1
1
1
00
00
00
1
0
1
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
—
—
(RDY/ BSY )
High-Z
High-Z
11
11
11
READ
WRITE
1
1
10
01
X
X
A6 A5 A4 A3 A2 A1 A0
A6 A5 A4 A3 A2 A1 A0
—
D15 – D0
D15 – D0
(RDY/ BSY )
27
27
WRAL
1
00
0
1
X
X
X
X
X
X
D15 – D0
(RDY/ BSY )
27
TABLE 1-4: INSTRUCTION SET FOR X8 ORGANIZATION (93XX56A OR 93XX56C WITH ORG = 0 )
Instruction
ERASE
SB
1
Opcode
11
Address
X A7 A6 A5 A4 A3 A2 A1 A0
Data In
—
Data Out
(RDY/ BSY )
Req. CLK
Cycles
12
ERAL
EWDS
EWEN
1
1
1
00
00
00
1
0
1
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
—
—
(RDY/ BSY )
High-Z
High-Z
12
12
12
READ
WRITE
1
1
10
01
X A7 A6 A5 A4 A3 A2 A1 A0
X A7 A6 A5 A4 A3 A2 A1 A0
—
D7 – D0
D7 – D0
(RDY/ BSY )
20
20
WRAL
1
00
0
1
X
X
X
X
X
X
X
D7 – D0
(RDY/ BSY )
20
? 2003-2011 Microchip Technology Inc.
DS21794G-page 5
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